1. Field of the Invention
The present invention relates to an analog semiconductor integrated circuit device which is required to have a high output voltage accuracy.
2. Description of the Related Art
In a semiconductor integrated circuit, a constant voltage circuit which outputs a constant voltage irrespective of the power supply voltage can be realized in a simplified manner at a low cost by, as illustrated in FIGS. 2A and 2B, connecting in series an enhancement type N-channel MOS field effect transistor (hereinafter referred to as NMOS) and a depression type N-channel MOS field effect transistor. Thus, the constant voltage circuit of this type is widely adopted.
In FIG. 2A, in an enhancement type NMOS 101, a source terminal and a body terminal which is connected to a P-type well region (hereinafter referred to as P-well) are connected to a ground terminal at the lowest potential in the constant voltage circuit, while a gate terminal and a drain terminal are connected to a source terminal of a depression type NMOS 102.
Further, in the depression type NMOS 102, a drain terminal is connected to a power supply voltage terminal at the highest potential in the constant voltage circuit, while a gate terminal is connected to the source terminal of the NMOS 102.
When such connection is made, first, the NMOS 101 operates in saturation because the potential of the gate terminal and the potential of the drain terminal are the same. With regard to the NMOS 102, when a voltage of a certain level or higher is applied to the drain terminal, the NMOS 102 operates in saturation. Because currents which pass through the respective NMOSs are the same, the following simple relational expression which expresses a state in which the saturation currents are balanced with each other is obtained:Kne(Vg1−Vtne)2=Knd(Vg2−Vtnd)2,  Eq. (a)where Kne, Vg1, and Vtne are the transconductance, the gate potential, and the threshold voltage of the NMOS 101, respectively, and Knd, Vg2, and Vtnd are the transconductance, the gate potential, and the threshold voltage of the NMOS 102, respectively.
From the above relational expression, an output value Vout of the constant voltage circuit is as follows:Vout=(Knd/Kne)1/2·|Vtnd|+Vtne.  Eq. (b)
As expressed above, Vout can be adjusted by the element characteristics of the respective NMOSs. In the case illustrated in FIGS. 2A and 2B, however, Vtnd and Knd are the threshold voltage and the transconductance determined under the back bias effect caused by the voltage Vout since the potential of the body terminal of the NMOS 102 is lower than the potential of the source terminal. To prevent the change in characteristics due to the back bias effect the body terminal will be connected to the source terminal. In this case, in order that the potentials of the respective P-well regions on which the NMOSs 101 and 102 are formed can be changed, it is necessary to select an N-type substrate as the semiconductor substrate to form the P-well regions each isolated by PN junction, and form the NMOSs 101 and 102 on the P-well regions, respectively. Except such case as mentioned above the circuit structure illustrated in FIGS. 2A and 2B is irrelevant to the polarity of the semiconductor substrate and is highly versatile.
Next, a method of manufacturing the above-mentioned conventional semiconductor integrated circuit device is schematically described with reference to FIG. 4. In the description, the same terminology is used as in FIGS. 2A and 2B.
First, a P-type semiconductor substrate or an N-type semiconductor substrate is prepared. After P-type impurities of boron (B) or BF2 are injected by ion implantation into desired regions in which the NMOSs are to be formed, thermal diffusion is performed to form the P-well regions (Step a). The amount of the injected impurities and the conditions of the thermal diffusion are selected so that the impurity concentration in the P-well regions lies between 1×1016 cm−3 and 1×1017 cm−3 and the depth of the P-well regions is several micrometers.
Next, in order to electrically isolate the elements from each other, LOCOS or the like is used to form an element isolation region (Step b).
Next, in order to adjust the threshold voltage of the enhancement type NMOS to be a desired value, P-type impurities of boron (B) or BF2 are injected by ion implantation into the region in which the enhancement type NMOS is to be formed (Step c).
Next, in order to adjust the threshold voltage of the depression type NMOS to be a desired value, N-type impurities of phosphorus (P) or arsenic (As) are injected by ion implantation into the region in which the depression type NMOS is to be formed (Step d).
Next, a gate oxide film of the enhancement type NMOS and the depression type NMOS is formed by thermal oxidation (Step e).
Next, in order to form gate electrodes of the enhancement type NMOS and the depression type NMOS, a poly-Si film is deposited and impurities at a high concentration are injected so as to attain 1×1019 cm−3 or higher by ion implantation or thermal diffusion, and patterning is carried out (Step f).
Next, in order to form source/drain regions and regions for giving potentials of P-well regions (referred to as body regions) under channels of the enhancement type NMOS and the depression type NMOS, impurities are injected by ion implantation. In this case, N-type high concentration impurities for forming the source/drain have a concentration 1×1019 cm−3 or higher and are arranged at a predetermined distance from the end of the gate electrode. On the other hand, N-type low concentration impurity regions of 5×1016 cm−3 to 5×1017 cm−3 are formed from the N-type high concentration impurity regions to the ends of the gate electrode, respectively. The N-type low concentration impurity regions operate to alleviate the electric field when a high voltage is applied (Step g).
Next, an insulating film which is an oxide film is deposited on the entire surface. After contact holes are formed at predetermined locations, in order to give potentials of the gates, sources, drains, and bodies of the respective NMOS elements, metal wiring is formed by sputtering and patterning a metal film (Step h).
Another exemplary conventional constant voltage circuit is described with reference to FIGS. 3A and 3B. In FIGS. 3A and 3B, the same NMOS element as illustrated in FIGS. 2A and 2B is used, and only the wiring method is changed. Specifically, a change is made so that the gate terminal of the depression type NMOS 102 is connected to the ground terminal which is the lowest potential in the constant voltage circuit. Because the gate voltage of the depression type NMOS 102 is shifted to a negative side by Vout, the output voltage and the current consumption can be remarkably reduced. The system of the above-mentioned constant voltage circuit is disclosed in, for example, Japanese Patent Application Laid-open No. 2008-293409.
When a conventional packaging is performed for encapsulating the above-mentioned semiconductor integrated circuit device including a low voltage circuit in a resin package, the following problem arises.
For example, when the threshold voltages and the transconductances of the enhancement type NMOS and the depression type NMOS vary in mass production, the output voltage of the constant voltage circuit varies. Further, the output voltage also fluctuates when the environment such as the temperature fluctuates. Accordingly, a method of realizing an NMOS element structure or a semiconductor integrated circuit system which can reduce fluctuations in output voltage of a constant voltage circuit is desired.